1. Field of the Invention
This invention relates generally to semiconductor manufacturing methods and more particularly to improved methods for forming an electrode contact portion of a base in bipolar semiconductor integrated circuits.
2. Description of the Prior Art
Generally, transistors in bipolar semiconductor integrated circuits are formed in respective islands that are electrically isolated from one another by utilizing, for example, p-n junction isolation, oxide isolation using selective oxidizing technique, or triple diffusion. In the ensuing description, explanation will only be given of a method for forming npn transistors by using oxide isolation. However, it should be understood that various isolation methods may be used instead of the specified example.
Referring to FIGS. 1A-1E, there are shown cross-sectional views of a semiconductor device structure in the prior art at primary steps in the manufacture thereof.
First of all, in FIG. 1A, a high impurity concentration layer 2 of n-type (or n.sup.+ -type) conductivity is selectively formed in a p-type (or p.sup.- -type) conductivity silicon substrate 1 having low impurity concentration; the layer 2 will be a collector buried layer. Next, an epitaxial layer 3 of n.sup.- -type conductivity is grown over the silicon substrate 1 and the layer 2.
Referring to FIG. 1B, an pad oxide layer (film) 101 and a nitride layer (film) 201 are formed over a predetermined region on the layer 3. A p-type layer 4 for the use of channel cutting (stopping) is formed by using nitride layer 201 as a mask and then a thick isolation oxide layer 102 is formed by a selective oxidizing technique using the nitride layer 201 as a mask at the same time as annealing the layer 4.
Referring to FIG. 1C, the pad oxide layer 101 is removed, as well as the nitride layer 201 used as the mask for the selective oxidizing. Next, an oxide layer 103 to be used as a protective layer during ion implantation is newly formed and a p.sup.+ -type layer 5 which will be an external base layer is formed using a photoresist layer (not shown) as a mask. Then the photoresist layer is removed and another photoresist layer 301 is formed in a predetermined pattern, which layer 301 is used as a mask when a p-type layer 6 is formed by ion implantation, layer 6 forming an active base layer.
Referring now to FIG. 1D, the photoresist layer 301 is removed and a passivation layer 401 of phospho silicate glass (PSG) is deposited, as shown. After a heat treatment for the purpose of annealing the layers 5 and 6 and sintering the PSG layer 401, an external base layer 51 and an active base layer 61 being in intermediate stages are formed, as shown. Then, windows (holes) 70 and 80 for contact with an emitter region and a collector region, respectively, are formed in the predetermined regions of the PSG layer 401 so that an n.sup.+ -type layer 7 which will act as an emitter layer and an n.sup.+ -type layer 8 which will act as a collector electrode contact portion are formed by ion implantation through the respective contact holes, as shown.
Last of all, referring to FIG. 1E, respective ion implanted layers are annealed and an external base layer 52 and an active base layer 62 are established, while an emitter layer 71 and a collector electrode contact layer 81 are formed, as illustrated. In the windows (contact holes), a metal silicide layer 501 is formed to prevent any penetration through the electrodes (for example, to prevent the reaction between Al and Si). Platinum silicide (Pt-Si) or palladium silicide (Pd-Si) may be used as the metal silicide 501. On such metal silicide layer 501, a base electrode wiring 9, an emitter electrode wiring 10 and a collector electrode wiring 11 are formed by using low resistance metal such as aluminum (Al).
Problem in the Prior Art
As is known in the art, the frequency characteristics of transistors depend on the base-to-collector capacitance and the base resistance. Accordingly, in order to improve the frequency characteristics of transistors, the base-to-collector capacitance and the base resistance are necessarily made small. In the aforementioned structure of the prior art, it is the external base layer 52 of p.sup.+ -type which is provided to decrease the base resistance.
On the other hand, the external base layer 52 causes the base-to-collector capacitance to increase.
Referring now to FIG. 2, there is shown a plan view of the pattern of a transistor produced in accordance with a prior manufacturing method. In FIG. 2, the base resistance depends on the distance (space) D.sub.1 from the emitter layer 71 to the contact hole 50 for the base electrode, as shown. Such distance is the sum of the distance between the base electrode wiring 9 and the emitter electrode wiring 10 and the distances of the electrode wirings 9 and 10 protruded over the respective holes 50 and 70. As a result, even if the distance between the electrode wirings is made small by improving the accuracy of photoetching (photolithography), the protruded distance cannot be changed. In addition, the base region between the emitter layer 71 and the boundary A of the oxide isolation layer shown in FIG. 2 is an inactive region and, therefore, causes the base-to-collector capacitance to increase. A walled emitter structure may be used to get rid of such nonactive region, in which structure the emitter layer 71 is in contact with the oxide isolation layer. However, the walled emitter structure has some problems which will be described.
Referring now to FIGS. 3A-3C, there are shown partial cross sectional views of FIG. 2 taken along line X--X. The problems associated with the walled emitter structure in the prior art will be described in connection with FIGS. 3A-3C.
Referring to FIG. 3A, there is shown a state in which a p-type impurity, here boron, is implanted using the photoresist layer 301 as a mask to form a base region. Then, it is necessary to remove the oxide layer 103 on the emitter region 7 to form a contact hole. In the wall emitter structure, however, the boundary A of the oxide isolation layer 102 is excessively etched away such as is shown in FIG. 3B when the oxide layer is removed. It follows from this that the emitter region is deepened as shown by B in FIG. 3C. As a result, the current amplification factor then gets out of control and a short circuit may arise between the collector and the emitter in the region B.
In order to lower the base resistance, a double base structure is often employed such as is shown in FIG. 4. In the prior art, however, the base-to-collector capacitance is somewhat increased because the base region is expanded due to the necessity to take out the base electrode.
Further, since the emitter-base junction is deeper than the surface of the external base region in the prior art, the current amplitude factor depends more on the current. To put it another way, since the current is absorbed due to, for example, recombination in interfaces (for example, interface between emitter and base regions), the current amplitude factor in a lower current region cannot be effectively controlled.